The present invention relates generally to digital-data receivers, and particularly to a channel-adaptive high-fidelity receiver for quickly synchronizing to a spread-spectrum signal.
Reliable, affordable communications is an essential component in any communication system. Spread-spectrum systems offer the flexibility of immediate (domestic) license-free operation in four distinct frequency bands (902-928 MHz, 2400-2483.5 MHz, 5150-5350, and 5725-5850 MHz) and can be deployed in several other bands to accommodate high data rates concurrently with high link integrity (low error rates), even in the presence of significant multipath effects and interfering signals. Two difficult but frequently encountered scenarios are the indoor and urban/suburban mobile radio environments; the typical multipath delay spreads range from 10 to 250 ns in the former case and 2 to 100 xcexcs in the latter (corresponding to 70% coherence-bandwidth ranges of 0.25-6 MHz and 0.6-30 kHz, respectively). This patent discloses additional advanced signal-processing methods tailored for spread-spectrum reception systems, but in some cases useful for non-spread systems as well, which support improved multipath-rejection capabilities for difficult applications (e.g., highly reflective environments or non-line-of-sight links), faster and more efficient synchronization, and improved tracking of spread-spectrum signals in dynamic environments.
A typical spread-spectrum receiver block diagram is shown in FIG. 1. The modulated signal enters the low-noise amplifier (LNA) via an antenna. This RF signal is then down-converted to a baseband signal using one or more mixing stages and corresponding local oscillators (LOs). The phase-locked loop (PLL) is necessary to fine-tune the LO(s) to the incoming RF signal. After filtering, the baseband signal enters a group of 2Nxe2x88x921 shift registers. (In some applications 2 sets of (2Nxe2x88x921)-length shift registers are used to improve correlation.) A parallel group of shift registers is loaded with a local copy of the spread spectrum code. The outputs of the two parallel groups of shift registers are exclusive-ORed together (single adder). The outputs of all the exclusive-ORs are summed, indicating the number of positions in which the two bit streams match or xe2x80x9cagreexe2x80x9d.
When the number of bit agreements exceeds a preset threshold, the signal is determined to be synchronized. The circuitry then tracks the incoming signal by making small adjustments to the frequencies and/or phases of the clock signals. The output of the bit-decision block is the baseband (despread) output data stream.
The number of mathematical operations required to synchronize the receiver correlator circuits to the typical spread-spectrum signal limits the practical range spreading-code lengths. Further, the number of operations also has a strong effect on the cost and complexity of the associated hardware. The novel synchronization approach contained in the instant invention reduces the time and hardware need to synchronize to a spread-spectrum signal and additionally facilitates direct down-conversion of the incoming RF signal to baseband, which in turn can alleviate the need for an intermediate-frequency (IF) stage in the receiver chain. This feature of the present approach can even further reduce receiver hardware complexity compared with the existing systems.
The art is replete with spread-spectrum receivers. For instance, U.S. Pat. No. 4,965,759 to Uchida et al. discloses a spread-spectrum receiver comprising a correlation pulse generator and associated circuitry for comparing peak values and thresholds based on those peak values to generate a correlation pulse. A similar approach using analog matched filters and a phase-dithered local-oscillator technique is shown in U.S. Pat. No. 4,017,798 to Gordy et al.
U.S. Pat. No. 5,216,691 to Kaufmann discloses a spread-spectrum receiver containing a bank of time-integrating correlators for correction of a received signal with a reference code and a downstream digital signal processor for evaluating results of the correlations. The resulting processed output approximately compensates for the multipath signal components produced by the terrestrial RF channel.
U.S. Pat. No. 5,774,494 to Sawahashi et al. discloses a frequency-error correction device for a spread-spectrum receiver which corrects a frequency error between a transmitter and receiver in a baseband signal range, thus obviating the need for a highly-accurate, highly-stable voltage-controlled oscillator.
U.S. Pat. No. 4,894,842 to Broekhoven et al. details a specialized spread-spectrum receiver for GPS satellites which employs direct sampling of the multiple received RF signals into a digitized baseband signal containing the multiple spread-spectrum modulations from the several satellites. The coded satellite data streams are then extracted sequentially using a single common digital-processing circuit block, thus providing a significant savings in hardware over previous parallel-channel code-division multiple-access (CDMA) decoding implementations.
U.S. Pat. No. 4,530,103 to Mosley, Jr. et al. discloses a baseband PN code-tracking method and apparatus utilizing a programmable numerically-controlled oscillator (NCO) which adjusts the phases of dual spread-spectrum code correlators according to a feedback signal produced by a post-detection baseband signal processor.
U.S. Pat. No. 5,903,593 to Ishiguro et al. describes a spread-spectrum receiver with faster synchronization and simpler circuitry than prior-art analog implementations by employing a digital synchronization-control scheme which uses a switchable multiple-index frequency-divider to alter the phase of the sync-reference signals. By rapid duty-cycle modulation of the divider indices, the average sync-timing errors are reduced.
All of the above receiver correlator-circuit implementations share at least one commonality in that they require the presence of at least 2Nxe2x88x921 shift registers, 2N binary adders, and a summing network with 2N inputs, or the equivalent in programmable logic devices. Thus, there remains room in the art for a receiver which will require fewer registers and gating and, thus, will require a smaller surface area when fabricated in an integrated-circuit (IC) chip implementation.
U.S. Pat. No. 4,744,094 to McCarren discloses a novel digital binary phase-shaft keyed (BPSK) demodulator employing an XOR gate, a generic phase-locked loop (PLL) for carrier regeneration, and a xe2x80x9cDxe2x80x9d-type flip-flop to decode and clock out the data stream. The BPSK demodulator circuit extracts the carrier frequency from the incoming signal by effectively canceling the data-induced phase inversions. When the input BPSK signal is near the center frequency of the VCO, the signal sampling occurs at approximately the middle of each cycle, or at approximately a 90-degree phase offset. A drawback of the realization is that the sampling will occur at points with much smaller or larger phase offsets than the nominal 90-degree figure as the signal input frequency moves farther away from the current VCO center frequency. The approach used in the instant invention avoids this issue (FIG. 7) by using a phase-frequency detector (PFD) 20, which has the property of possessing a zero-degree phase offset for any frequency when the PLL is in a locked status. (A thorough discussion of PFDs may be found in B. Razavi, RF Microelectronics, Prentice-Hall, 1998, pp. 258-261). The VCO output 52 is the carrier frequency, and the output of the XOR gate 18 is the baseband chip data signal. The clock recovery circuit 24, as described in D. H. Wolaver, Phase-Locked Loop Circuit Design, Prentice-Hall, 1991, pp.211-237, is included to properly align the clock signal with the chip data for use in the correlator circuitry 26 and to reduce jitter in the clock signal.
Another aspect of the prior art lies in the implementations of RF channel equalizers to reduce data errors. U.S. Pat. Nos. 5,444,739 and 5,563,911 to Useugi et al. disclose improvements to prior-art combinations of forward and feedback-type transversal channel-equalization filters used in digital communications systems such as GSM cellular phones, via selective control of the filter topologies according to estimated channel impulse responses. When fewer significant multipath components are detected in the received signals, the filters are simplified in topology (number of branches), thus reducing power consumption in the receiver. U.S. Pat. No. 5,402,445 to Matsuura discloses a decision-feedback equalizer (DFE) implemented with a parallel-distributed group of tap-coefficient adders rather than the usual serial topology; this provides higher speed operation than with prior-art approaches. U.S. Pat. No. 4,747,105 to Wilson et al. discloses a method for linear feedback digital-data sequence estimation with concurrent error correction. By comparing an incoming sequence (presumed to be generated by a known linear-feedback shift-register [LFSR] technique) to its predicted values and a calculated set of parity bits derived from specific terms in the sequence""s known defining polynomial, the received values are tested for correctness and corrected as necessary, while minimizing the probability of false correlation detects. This technique, however, is intended only for LFSR-derived sequences and is thus not useful for more generalized systems employing convolutional coding and the like. A more popular scheme is the maximum-likelihood sequence-estimation detector, commonly known as the Viterbi decoder, after its inventor. Numerous all-digital implementations of Viterbi-type data decoder circuits have been described in the literature, such as U.S. Pat. No. 5,307,374 to Baier, U.S. Pat. No. 5,887,007 to Iwata et al., U.S. Pat. No. 5,923,713 to Hatakeyama, and U.S. Pat. No. 5,881,106 to Cartier, each of which describe varying reduced-hardware implementations of Viterbi processors, but configured with totally digital circuitry or also using software-programmable logic.
A technique more relevant to the instant case employing a classic form of layered neurons in an analog-implemented artificial neural-network (ANN) format, optionally in conjunction with a digital control and sequencing logic block, to compute the Viterbi-algorithm path metrics and select the maximum-likelihood output sequence is described in U.S. Pat. No. 5,548,684 to Wang et al. (This implementation will be examined in much greater detail in the following sections). This invention, however, is targeted exclusively at the data-decoder application; the use of similar signal-processing techniques for optimizing adaptive RF channel equalizers is not mentioned. The circuit topology of the ""684 case, although effective, is significantly different and more complex than the specialized CMOS analog array-processing circuitry embodied in the instant invention. In general, all the aforementioned data equalization and error-correction schemes require significant amounts of digital logic to perform their functions; in contrast, the instant invention instead relies principally on area- and power-efficient analog and mixed-signal CMOS IC-based circuitry to handle these processing tasks.
It is an object of this invention to provide a channel-adaptive high-fidelity receiver for quickly synchronizing to a spread-spectrum signal.
It is also an object of this invention to provide a channel-adaptive high-fidelity receiver which primarily uses mixed-signal blocks on the same CMOS chip.
It is a further object of this invention to provide a channel-adaptive high-fidelity receiver which for the spread-spectrum code synchronization function requires only 2N digital shift registers and a minimal number of gates.
It is an even further object of this invention to provide a channel-adaptive high-fidelity receiver utilizing mixed-mode (analog plus digital) circuitry for the transversal (delay-line) equalizers and a Viterbi-type maximum-likelihood data decoder for higher receiver system performance, concurrently with lower power and significantly reduced IC footprint.
It is an even further object of this invention to provide a channel-adaptive high-fidelity receiver utilizing mixed-mode circuitry for the transversal (delay-line) equalizers and a Viterbi-type data decoder which have been specifically configured to be operable at the chipping rate of the received spread-spectrum signals to provide substantially greater multipath immunity, particularly in indoor and mobile communications environments.
It is an even further object of this invention to provide a channel-adaptive high-fidelity receiver which only requires internal logic clock rates equivalent to the spread-spectrum bit (xe2x80x9cchippingxe2x80x9d) rate rather than at N times that speed.
This and other objects of the invention are achieved by a fast-synchronizing receiver comprising an equalizer configured for manipulating a signal; a detector in communication with the equalizer; a filter in communication with the detector; a decoder in communication with the filter; an oscillator in communication with the filter; a gate for receiving the manipulated signal; a circuit portion for synchronizing and tracking the manipulated signal; a summing circuit in communication with the digital circuit portion; and, an output gate.